ASML announced plans to collaborate with its major customers to produce advanced lithography tools capable of printing larger data‑center chips, a move that could boost chip manufacturing capacity for companies like Nvidia and Intel.
ASML, the Dutch lithography giant, said it will partner with its biggest customers to develop next‑generation extreme ultraviolet (EUV) tools that can print larger data‑center chips, a step that could expand manufacturing capacity for firms such as Nvidia and Intel.
Why larger chips matter
Larger dies enable higher yields per wafer, reducing the cost per transistor and accelerating the rollout of high‑performance compute platforms needed for AI and cloud workloads.
Current EUV machines are optimized for the most advanced nodes, but they face challenges when scaling up to the 200‑millimeter or larger substrates required for next‑generation data‑center products.
Collaboration framework
ASML will work closely with its major chipmaking partners to co‑design the optical and illumination systems, sharing road‑map insights and testing prototypes in pilot lines.
The joint effort is expected to align tool development timelines with the product cycles of leading silicon designers, ensuring that the new equipment is ready when the market demand peaks.
Potential impact on the supply chain
If successful, the larger‑chip EUV tools could increase wafer output by up to 20 % for participating fabs, easing the current capacity constraints that have tightened the supply of high‑end GPUs and CPUs.
Analysts note that a boost in production capacity could also temper price pressures on advanced silicon, benefiting downstream manufacturers and end‑users alike.
- Higher yields per wafer
- Reduced cost per transistor
- Accelerated AI hardware deployment
- Improved supply stability for data‑center chips
We see a clear opportunity to unlock more value from each wafer by expanding the size of the chips we can produce, said an ASML spokesperson.
The initiative underscores ASML’s strategic shift toward broader tool portfolios, complementing its existing focus on sub‑10‑nanometer nodes.
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