Alphabet’s new chip, "Frozen v2", will hardwire Gemini’s architecture into silicon, promising a 6‑10× efficiency boost over current TPUs.
Alphabet is engineering a new AI accelerator called “Frozen v2” that will embed the Gemini architecture directly into silicon, aiming to deliver a six‑to‑ten‑fold efficiency improvement over its current TPU lineup.
What is Frozen v2?
Frozen v2 is the next generation of custom ASICs designed by Alphabet’s hardware team. Unlike previous TPUs that run Gemini models as software on a programmable fabric, the new chip hard‑wires the core computational graph of Gemini into the silicon itself.
Key design goals
- Integrate Gemini’s transformer kernels at the transistor level
- Reduce data movement between memory and compute units
- Lower power consumption per inference operation
- Scale performance for both training and inference workloads
By eliminating the software‑to‑hardware translation layer, Alphabet expects the chip to achieve up to ten times the energy efficiency of its current TPU v4 generation, according to internal projections.
Impact on Alphabet’s AI ecosystem
If the performance claims hold, Frozen v2 could accelerate the rollout of Gemini‑based services across Google Cloud, Search, and Assistant, offering faster response times while cutting operational costs.
The chip also signals a broader industry shift toward embedding large‑scale model architectures directly into hardware, a trend that could reshape how AI workloads are deployed at scale.
For more details, see the MLQ.ai coverage of Alphabet’s Frozen v2 AI chip.